Important and constant goals of the computer industry include higher performance, lower cost, increased miniaturization of components, and greater packaging density for integrated circuits (“ICs”). As new generations of IC products are released, the number of IC devices needed to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these IC products increases. For example, on the average there is approximately a 10 percent decrease in components required for every IC product generation over a previous generation having equivalent functionality.
Semiconductor package structures continue to become thinner and ever more miniaturized. This results in increased component density in semiconductor packages and decreased sizes of the IC products in which the packages are used. These developmental trends are in response to continually increasing demands on electronic apparatus designers and manufacturers for ever-reduced sizes, thicknesses, and costs, along with continuously improving performance.
These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cell phones, hands-free cell phone headsets, personal data assistants (“PDAs”), camcorders, notebook personal computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large-scale integration (“LSI”) packages incorporated into these devices, as well as the package configurations that house and protect them, must also be made smaller and thinner.
Many conventional semiconductor chip or die packages are of the type having a semiconductor die molded into a package with a resin, such as an epoxy molding compound. The packages have a leadframe whose out leads are projected from the package body to provide a path for signal transfer between the chip and external devices. Other conventional package configurations have contact terminals or pads formed directly on the surface of the package.
In IC packaging, in addition to component size reduction, surface mount technology (“SMT”) has demonstrated an increase in semiconductor chip density on a single substrate (such as a printed circuit board (“PCB”)) despite the reduction in the number of components. SMT is a method used to connect packaged chips to substrates. With SMT, no through-holes in the substrate are required. Instead, package leads are soldered directly to the substrate surface. This results in more compact designs and form factors, and a significant increase in IC density and performance. However, despite these several reductions in size, IC density continues to be limited by the space or “real estate” available for mounting chips on a substrate.
One method to further increase IC density is to stack semiconductor chips vertically. Multiple stacked chips can be combined into a single package in this manner with a very small surface area or “footprint” on the PCB or other substrate. This strategy of stacking IC components vertically has in fact been extended to the stacking of entire packages upon each other. Such package-on-package (“PoP”) configurations continue to become increasingly popular as the semiconductor industry continues to demand semiconductor devices with lower costs, higher performance, increased miniaturization, and greater packaging densities. Continuing substantial improvements in PoP technology are anticipated to address these requirements.
Unfortunately, limitations of current PoP stacking techniques can interfere with the ready incorporation and utilization of existing die and package configurations. It can reduce the effective reliability of the package due to movement of the packages with changes in temperature. The movement or warping of package substrates can damage die exposed on a base substrate or fracture interconnects between the substrates.
For example, in a previous PoP configuration, the base package has bonding pads on the top side that allow surface mounting of a top or second package. In order to successfully and effectively mount the top package on the base package, it is necessary to have sufficient clearance or “headroom” between the packages for accommodating structures, such as dies or a mold cap, on the top of the base package. However, typically due to cost and efficiency considerations, the only physical structure connecting the top package and the base package is the electrical interface between them. This electrical interface is usually a solder ball matrix on the bottom of the top package that aligns with bonding pads on the top of the base package.
Previous techniques employing such solder ball matrices usually afford only a small space or stand-off provided by the nominal height of the solder balls. This limits the available height for the base package components on the top of the base package, such as one or more semiconductor dice. Since the primary goal of the integration is to reduce the size of the package clearances are held to a minimum.
The problem of limited space between the base package and the top package increases the critical dimensions and manufacturing difficulty of the PoP. The integrated circuit die on the base package, if exposed, may be damaged during or after assembly by the movement of the two packages caused by different rates of thermal expansion and rigidity.
Thus, while a need still remains for smaller, thinner, lighter, less-expensive integrated circuit PoP systems, a great need also remains for PoP systems that simplify the assembly process and help address the warping issue that can damage the integrated circuit die of the base package. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.